Memory devices, such as DRAM devices, have a large number of signal terminals for receiving command, address and write data signals and for transmitting read data signals. The large number of terminals is generally required for memory devices used in most electronic systems, such as computer systems, that include a large number of such memory devices.
The command signals that are applied to memory devices are well-established and have been in common use for many years. Not only are users familiar with such commands, but devices used with memory devices, such as memory controllers, are specifically designed with such commands in mind. It would therefore be inconvenient to use or sell memory devices that use a command set that is different from this commonly used set of commands. Command signals for dynamic random access memory (“DRAM”) devices, for example, receive a number of command signals at respective terminals. These command signals are generally clock enable CKE#, chip select CS#, write enable WE#, row address strobe RAS# and column address strobe CAS# signals, where the “#” indicates the signal is active low.
It would be desirable to reduce the number of signals and corresponding terminals that memory devices use to interface with other devices, such as processors or memory controllers. However, the currently used command signals are generally considered necessary to implement all of the desired functionality of memory devices. Therefore, it has been considered impractical to reduce the number of command signals that must be provided to memory devices.